1. Field of the Invention
The present invention relates to a comparator having two differential amplifiers and a latch circuit, which can be applied to an analog/digital (A/D) converter.
2. Description of the Related Art
Conventionally, a comparator includes a differential amplifier and a latch circuit for latching the outputs of the differential amplifier, which, however, requires a high power consumption.
In order to reduce the power consumption, a first prior art comparator includes a prestage differential amplifier in front of the conventional comparator (see: M. Hotta et al., "A 150-mV 8-Bit Video-Freguency A/D Converter", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 2, pp. 318-323, April 1986). This will be explained later in detail.
In the first prior art comparator, however, the operation speed of the latch stage cannot be increased, and therefore, the operation speed of the comparator cannot be increased.
In order to increase the operation speed, a second prior art comparator includes emitter-follower type buffers connected to the latch stage (see: T. Wakimoto et al., "Si Bipolar 2-GHz 6-bit Flash A/D Conversion LSI", IEEE Journal of Solid-State Circuits, vol. 23, No. 6, December 1988). This will be explained later in detail.
In the second prior art comparator, however, the operation speed of the latch stage is still low, and therefore, the operation speed of the comparator is still low.